New in VX.2.12 is the ability to simulate and plot DDR5 eye diagrams down to a probability of 1e-16 in both batch and interactive simulations. Hyperlynx offers full workflows for both pre-layout design exploration and post-route verification of DDR-based interfaces. Power Delivery Network (PDN) design & verification.In VX.2.12 improvements have been made across the following areas: To learn more about HyperLynx DDRx, visit.The new VX.2.12 release of HyperLynx delivers state of the art simulation capabilities to mainstream designers by combining advanced modeling and simulation techniques with automated workflows that guide users through analysis step by step. Pre-route analysis to drive design restraints Post-route analysis / full interface level verification Benefits include:Īutomated workflow using wizards to guide through process HyperLynx DDRx provides powerful integrated signal integrity, crosstalk, and timing analysis that significantly reduces design and debug cycles for PCBs with DDR memory. Powerful, automated HyperLynx DDRx simulation
With HyperLynx DDRx, you can fast track design decisions, improve engineering efficiency, and accelerate time to market. HyperLynx streamlines DDRx design by dramatically reducing simulation setup time while providing accurate detailed results that include the effects of lossy transmission lines, reflections, impedance changes, vias, ISI, crosstalk, via-tovia coupling, SSN, and timing delays. Traditional signal integrity batch-mode tools just aren’t up to the task.
Complete validation of DDRx interfaces requires hundreds of signal integrity simulations and thousands of detailed measurements, followed by a comprehensive analysis of all signal quality requirements and signal/group timing relationships. DDR interfaces are some of the most complicated parallel interfaces in use today.
0 kommentar(er)
